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High-Level Synthesis For RISC-V
High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing...
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ML And UVM Share Same Flaws
A number of people must be scratching their heads over what UVM and machine learning (ML) have in common, such that they can be described as having the same flaws. In both cases, it is a flaw of...
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Verification Scorecard: How Well Is The Industry Doing?
Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike...
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The Next Incarnation Of EDA
The EDA industry has incrementally addressed issues as they arise in the design of electronic systems, but is there about to be a disruption? Academia is certainly seeing that as a possibility, but not...
View ArticleEfficient Verification Of Mixed-Signal Series IP Using UVM
Interface IP are an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a...
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Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s...
By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera...
View ArticleUnderstanding UVM Coverage For RISC-V Processor Designs
Attempting to achieve complete RISC-V verification requires multiple methodologies employing a wide range of relevant tools, including: • Coverage driven simulation based on UVM constrained random...
View ArticleUniversal Verification Methodology Coverage For Bluespec RISC-V Cores
Attempting to achieve complete RISC-V verification requires multiple methodologies, one of which is coverage driven simulation based on UVM constrained random methods and complaint with the Universal...
View ArticleWhat Happened To Portable Stimulus?
In June 2018, Accellera released the initial version of the Portable Test and Stimulus Standard (PSS), a new verification language that was slated to be the first new abstraction defined within EDA for...
View ArticleVerification Tools Straining To Keep Up
Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing...
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