Blog Review: Sept. 9
Doulos’ John Aynsley explains in a guest blog for Aldec why FPGA designers need to know SystemVerilog and UVM. Might be time to increase the coffee budget. Speaking of verification, Cadence’s Frank...
View ArticleAppetite For Services Grows
Semiconductor service revenues have been growing for the past year, fueled by complex thermal and power issues at advanced nodes, the difficulty of integrating more and more IP blocks, and far more...
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HW Vs. SW: Who’s Leading Whom?
In the past, technologies were developed in the software world that have languished until they were taken up by the hardware community. Then they were refined and polished and became fully integrated...
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U.V.M. Spells Relief
Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief....
View ArticleA History of (Premature) Optimization
I saw some material shared from DVCon Europe last month that suggested a competition brewing between shift left and agile in semiconductor development. As someone who’s been following shift left...
View ArticleVerification Grows Up
Semiconductor Engineering sat down with a group of verification experts to see how much progress has been made in solving issues associated with the profession. Panelists included Mike Baird, President...
View ArticleBeyond UVM Registers — Better, Faster, Smarter
Adoption of SystemVerilog UVM is growing stronger. Verification teams are expanding their knowledge with respect to UVM features and capabilities. These verification teams are using the UVM Register...
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Still Time to Blow Up UVM
Blowing up UVM is something I ran on my own blog a few years ago. Considering not much has changed with respect to UVM – that it continues to dominate verification circles – I figured it’s a discussion...
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UVM: It’s Organized And Systematic
One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep...
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Verification Facing Unique Inflection Point
The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory,...
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UVM Register Layer: The Structure
I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full...
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Making Way For Register Specification Software
No one gives much thought to the heating, ventilation and air conditioning registers in the house –– typically, two in each room, one for supply, the other for return. That is, until the lever in each...
View ArticleBridging the IP Divide
IP reuse enabled greater efficiency in the creation of large, complex SoCs, but even after 20 years there are few tools to bridge the divide between the IP provider and the IP user. The problem is that...
View ArticleGoing Open Source
Open Source often is thought of as an alternative to commercial software licensed using fairly typical business models. For example, variants of open source Linux supplied by companies such as Red Hat...
View ArticleOpen Standards For Verification?
The increasing use of verification data for analyzing and testing complex is raising the stakes for more standardized or interoperable database formats. While interoperability between databases in chip...
View ArticleFormal Confusion
Semiconductor Engineering sat down to discuss the right and wrong ways to apply formal verification technology with Normando Montecillo, associate technical director at Broadcom; Ashish Darbari,...
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DAC Day Three: UVM, Machine Learning And DFT Come Together
The industry and users have a love/hate relationship with UVM. It has quickly risen to become the most used verification methodology and yet at the same time it is seen as being overly complex,...
View ArticleReducing Design Risk With Testbench Acceleration
Part 1 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three...
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Can Verification Meet In The Middle?
Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller...
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The UVM Configuration Database
When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future. A...
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