Week In Review: Design, Low Power
Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal...
View ArticlePortable Stimulus And Digital Twins
It has been a year since Accellera’s Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it,...
View ArticleWeek In Review: Design, Low Power
Inphi Corporation and Synopsys finalized the acquisition of eSilicon. Synopsys acquired certain IP assets from eSilicon, including TCAMs and multi-port memory compilers, as well as its Interface IP...
View ArticleMaking Sure RISC-V Designs Work As Expected
The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than...
View ArticleContext-Aware Debug
Moses Satyasekaran, product manager at Mentor, a Siemens Business, examines the growing complexity of debug, which now includes software, power intent and integration, multiple clocking and reset...
View ArticleWhy Is PSS So Important?
Robert Hoogenstryd, product marketing manager at Mentor, a Siemens Business, talks about the new testbench verification language standard, what are the big advantages of using PSS, what kinds of...
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Simulation: Balancing Speed And Debug
There’s an old saying about simulation: “It’s all about the need for speed.” Simulation is the core technology for functional verification of semiconductors, and the demand for higher runtime...
View ArticleUsing Processor Trace At The System Level
The race to process more data faster using less power is creating a series of debug challenges at the system level, where developers need to be able to trace interactions across multiple and often...
View ArticleBetter UVM Debug with Visualizer
The post Better UVM Debug with Visualizer appeared first on Semiconductor Engineering.
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A Different View On Debugging
The classic approach to improve an engineering task that is becoming too complex due to its size and detail is to raise the abstraction of design representation. In this way we plan cities, build...
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The Increasingly Ordinary Task Of Verifying RISC-V
As RISC-V processor development matures and its usage in SoCs and microcontrollers grows, engineering teams are starting to look beyond the challenges of the processor core itself. So far, the majority...
View ArticleWeek In Review: Design, Low Power
Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal...
View ArticleBetter UVM Debug with Visualizer
The post Better UVM Debug with Visualizer appeared first on Semiconductor Engineering.
View ArticleWeek In Review: Design, Low Power
Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal...
View ArticleClik here to view.
Methodology Vs. Problem-Solving
When I was 18, I bought a Vespa ’67: the famous Italian scooter. It was already very old then, totally beaten-up, but luckily I had a friend who owned an auto-repair shop, and he was kind enough to...
View ArticleOpen-Source Verification
Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification...
View ArticleUniversal Verification Methodology Running Out Of Steam
For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, more...
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How UVM Callbacks Simplify Assertion Validation
By Akshay Sarup and Mark Olen Assertions bring immediate benefits to the whole design and verification cycle; thus any challenges engineers face in coding and testing them are worth resolving. When a...
View ArticleNew Uses For Assertions
Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification...
View ArticleBlog Review: Oct. 7
In a blog for Arm, University of Southampton PhD student Sivert Sliper looks at how energy-driven and intermittent computing could be used to power trillions of IoT devices and introduces a...
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