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It’s Show Time
It’s been a busy season. The weather has warmed here in the desert and as the trees and greenery enliven in spring, The whole industry is bursting with activity. From DVCon to the International...
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Safety Plus Security: A New Challenge
Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry’s attention. And...
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Hybrid Emulation
Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for Cadence; Russ...
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Verification Unification
Semiconductor Engineering brought together industry luminaries to initiate the discussion about the role that formal technologies will play with the recently released early adopter’s draft of Portable...
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Portable Stimulus Status Report
The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two...
View ArticleEfficient Verification Of Mixed-Signal SerDes IP Using UVM
Interface IP is an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a host...
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System Coverage Undefined
When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it’s the one verification engineers lose sleep over. Exhaustive coverage has not...
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Inside UVM
We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t...
View ArticleUVM Can Kill You. More News At 11
Ok. I agree. Not a great title. I don’t like it either. Some pretty aggressive clickbait, I know. But it’s got the quick hit, newsy cliffhanger feel that makes you want to tune in anyway, doesn’t it? I...
View ArticleWhich Verification Engine?
Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at Mentor, a Siemens Business; Frank Schirrmeister, senior...
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Is Verification Falling Behind?
Every year that Moore’s Law is in effect means that the verification task gets larger and more complex. At one extreme, verification complexity increases at the square of design complexity, but that...
View ArticleReflection On 2017: Design And EDA
People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the...
View ArticleBlog Review: Jan. 24
Mentor’s Rich Edelman shares some tips for debugging complex UVM testbenches containing multiple agents, multiple checkers, and new HDL. Synopsys’ Prasad Subudhi K. S. explains the PCIe PIPE 4.4.1...
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Predictions: Methodologies And Tools
Predictions are divided into four posts this year. Part one covered markets and drivers. The second part looked at manufacturing, devices and companies and this part will cover methodologies and tools....
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DVCon Committee Picks
A typical development team contains more verification engineers than design engineers, and that skew is getting wider. You can expect the trend to increase given that verification teams are now getting...
View ArticleBlog Review: Jan. 31
Cadence’s Paul McLellan looks back at where TSMC was 30 years ago and the founding philosophy that made the foundry and fabless model work. In a video, Mentor’s Colin Walls considers how to make the...
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Using Data Mining Differently
The semiconductor industry generates a tremendous quantity of data, but until very recently engineers had to sort through it on their own to spot patterns, trends and aberrations. That’s beginning to...
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Inside UVM, Take Two
In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In...
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Executive Insight: Wally Rhines
Wally Rhines, president and CEO of Mentor, a Siemens Business, sat down with Semiconductor Engineering to discuss a wide range of industry and technology changes and how that will play out over the...
View ArticleGoing Deep Or Broad With Formal?
Whether to apply Formal Verification technology to semiconductor design broadly or deeply is a tough question. It hinges on what is the best way to achieve maximum ROI. Do you want to identify hard to...
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